1. Field of the Invention
The present invention relates to a CCD solid image capturing element and a method for manufacturing the same. In particular, the present invention relates to suppression of power consumption in an output section.
2. Description of the Related Art
FIG. 4 schematically shows a structure of a CCD solid image capturing element using a frame transfer method. Specifically, a CCD solid image capturing element using a frame transfer method comprises an image capturing section i, a storage section s, a horizontal transfer section h, and an output section d.
The image capturing section i generates information charges in a two-dimensional array and transfers the charges at a high speed to the storage section s. The information charges are stored in the storage section s and also transferred to the subsequent horizontal transfer section h for every pixel row. The information charges are then transferred to the output section d for each pixel. The output section d converts the information charge for one pixel into a voltage having a corresponding value. A change in the voltage value is output as a CCD output.
FIGS. 5 and 6 are cross sectional views showing major elements of a conventional CCD solid image capturing element. In particular, FIG. 5 is a cross sectional view along the charge transfer direction in a vertical shift register, showing an output end of a vertical shift register (V-REG) constituting the storage section s and its nearby portions. FIG. 5 additionally shows a horizontal transfer section h coupled to the output end of the storage section s. FIG. 5 is a cross sectional view along the charge transfer direction in the horizontal shift register, showing an output end of the horizontal shift register (H-REG) and its nearby portions. FIG. 5 additionally shows a floating diffusion layer (FD) 18 and a reset drain (RD) 20, which constitute a part of the output section d.
Specifically, in an N-type silicon substrate 2, an N-well (NW) 4, a P-well (PW) 8 or 10, and an N-type layer (Nsub) 6 are formed, in that order downward from the surface of the silicon substrate 2, through ion implantation and subsequent diffusion. Specifically, the N-well 4 is an N-type layer formed on the surface of the substrate, and the P-well 8 or 10 is a P-type layer underlying the N-well 4. The N-type layer 6 is apart of the original substrate.
Referring to FIG. 5, an information charge is sequentially transferred in the rightward direction in the drawing through potential wells formed in the N-well 4 in the vertical shift register until it is read into a potential well formed below an electrode 14-1 in the horizontal shift register. Meanwhile, referring to FIG. 6, the information charge is transferred in the leftward direction in the drawing through potential wells formed in the N-well 4 in the horizontal shift register until it finally reaches, passing under the output gate (OG) 16, the floating diffusion layer 18.
The floating diffusion layer 18 is an N+ diffusion layer and its potential is set at a reset drain potential VRD of the reset drain 20 when the adjacent reset gate (RG) 22 is turned on. When an information charge is supplied from the horizontal shift register to the floating diffusion layer 18, the potential of the floating diffusion layer 18 is caused to vary according to the amount of the charge supplied from the horizontal shift register. This potential variation is detected and amplified by an output amplifier 30, which in turn outputs a voltage VOUT as a CCD output.
The output amplifier 30 also is formed in the semiconductor region on the surface of the silicon substrate 2. Specifically, the drain and source of the MOS transistor 32, 34 of the output amplifier 30 are formed by N+ diffusion layers on the surface of the substrate 2 and a channel formed in the semiconductor substrate region between the drain and the source is controlled using a gate electrode which is formed by poly-silicon electrode layers on gate oxide films.
When the P-well 10 and the N-well 4 are formed in the N-type substrate 2, as described above, an NPN structure is formed in the substrate. In this structure, redundant charges on the surface of the substrate can be discharged into the depths in the substrate.
FIG. 7 schematically shows a potential distribution downward into the substrate. In the drawing, the abscissa corresponds to the distance in the depth direction of the substrate with its leftward direction corresponding to the surface of the substrate 2 (that is, the gate oxide film side) and its rightward direction corresponding to the back side of the substrate 20. The ordinate of the drawing corresponds to a potential with its lower direction corresponding to a positive potential direction (in which, in this embodiment, a potential becomes deeper) . The potential distribution curve 42 corresponds to the horizontal transfer section h (H-REG), while the potential distribution curve 40 corresponds to the image capturing section i and the storage section s.
As shown, because a predetermined positive voltage Vsub (for example, 5V) and a positive voltage VS corresponding to an on stage (for example, 5V) are applied to the substrate and the transfer electrode, respectively, in a vertical shift register constituting the image capturing section i or the storage section s, a potential barrier is formed in the P-well 8 and a potential well is formed in the N-well 4. Because the electron tends to flow from a place with a shallower potential to a place with a deeper potential in the silicon substrate 2, that is, from a projected portion of a potential distribution curve to a recessed portion thereof, in a normal operation, the information charge in a potential well in the N-well 4 is blocked by the potential barrier in the p-well 8 from flowing into the depths in the substrate 2.
When a higher substrate voltage Vsub or a lower positive voltage VS is applied, the potential well in the N-well 4 becomes shallower and the potential barrier in the P-well 8 becomes lower, which allows the information charge in the N-well 4 to be discharged into the depths of the substrate. In an electronic shutter operation, for example, a voltage to be applied to the substrate side or the transfer electrode may be manipulated in such a manner that information charge in the image capturing section i or the storage section s could be instantly discharged therefrom to thereby reset the section.
In a vertical over flow drain (VOD) structure as described above, an excessive information charge in a light receiving pixel in the image capturing section i can be discharged, over the potential barrier in the P-well 8, into the depths in the substrate. Therefore, a problem known as “blooming”, that is, leakage of information charge to other pixels can be prevented.
It should be noted that FIG. 7 additionally shows a potential distribution curve 44 which represents a potential in a region below the reset drain 20 of the output section d and the drive transistor 32 of the output amplifier 30. This region exhibits the potential characteristic as shown, as a power voltage VDD (for example, 5V) is supplied to the reset drain 20 of the output section d and a drain diffusion layer of the drive transistor 32.
The above described discharging of information charge into the depths of a substrate is mainly advantageous in the image capturing section i and the storage section s, and not in the horizontal transfer section h and the output section d. Therefore, conventionally, after p-type dopant ion is doped over the entire surface of a substrate where an image capturing section i, a storage section s, a horizontal transfer section h, and a output section d are to be formed, p-type dopant ion is further doped only to a region where the horizontal transfer section h and the output section d are to be formed while covering, using a mask, a region where the image capturing section i and the storage section s are to be formed.
Consequently, concentration of p-type dopant in the P-well 10 below the horizontal transfer section h and the output section d results in higher than that in the P-well 8 in the image capturing section i and the storage sections. An example of such a difference in dopant concentration is shown in FIG. 7. That is, a higher potential barrier is formed in the P-well in the horizontal shift register (curve 42) than in the vertical shift register (curve 40). This difference in the height of the potential barrier is resulted from the difference in dopant concentration between the relevant regions.
With this structure, it is possible to arrange, by controlling the substrate voltage Vsub or the like, such that information charge is discharged into the depths in the substrate only in the vertical shift register but not in the horizontal shift register.